Protel Design System Design Rule Check
PCB File : C:\VIRGIL\AAA__JOB\ALTIUM\STM\Projets\MB1918C\BASE\MB1918C\01-Design-sources\Altium_Designer\MB1918.PcbDoc
Date     : 05/07/2023
Time     : 03:15:02

Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=0.13mm) (InNetClass('NC__USB-90R')),(All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=0.22mm) (InNetClass('NC_S50R_FLASH')),(All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=Yes) (InPadClass('PADS_LINK_CC')),(InPadClass('PADS_LINK_CC'))
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Width Constraint (Min=0.12mm) (Max=10mm) (Preferred=0.12mm) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=0.14mm) (Max=0.17mm) (Preferred=0.17mm) (InNetClass('NC_S50R_FLASH'))
Rule Violations :0

Processing Rule : Routing Layers(All)
Rule Violations :0

Processing Rule : Routing Via (Templates Used To Check Via: v60h30m35mx35) (All)
Rule Violations :0

Processing Rule : Routing Via (Templates Used To Check Via: v40h15m20mx20) (WithinRoom('RoomDefinition_STLink')and TouchesRoom('RoomDefinition_STLink'))
Rule Violations :0

Processing Rule : Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.13mm) (Max=0.13mm) (Prefered=0.13mm)  and Width Constraints (Min=0.11mm) (Max=0.15mm) (Prefered=0.15mm) (InDifferentialPairClass('PC__USB-90R'))
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=0.42mm) (InDrillLayerPair('Top Layer - Bottom Layer')),(InDrillLayerPair('Top Layer - Bottom Layer'))
Rule Violations :0

Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0

Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0mm, Vertical Gap = 0mm ) (All),(All) 
Rule Violations :0

Processing Rule : Height Constraint (Min=0mm) (Max=40mm) (Prefered=40mm) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mm) (Max=5mm) (Prefered=5mm) (OnBottomLayer and WithinRoom('HMAX 5MM'))
Rule Violations :0


Violations Detected : 0
Waived Violations : 0
Time Elapsed        : 00:00:04