# Design Rule Verification Report

Date: |  | 12/02/2026
Time: |  | 16:44:55
Elapsed Time: |  | 00:00:00
Filename: |  | C:\Subversion\_Boards\MB2439_STM32WBA2_CSP37_SMPS_USB_IPD_4L\Trunk\01-Design_Source\Altium_Designer\MB2439.PcbDoc
Warnings: |  | 0
Rule Violations: |  | 0

## Summary

Warnings | Count
--- | ---
Total | 0

Rule Violations | Count
--- | ---
Clearance Constraint (Gap=0.127mm) (InNetClass('RF')),(All) | 0
Clearance Constraint (Gap=0.1mm) (All),(All) | 0
Clearance Constraint (Gap=0.075mm) (WithinRoom('CSP')),(All) | 0
Clearance Constraint (Gap=0.16mm) (InNetClass('DIFF90')),(All) | 0
Clearance Constraint (Gap=0.1mm) (WithinRoom('IPD')),(All) | 0
Short-Circuit Constraint (Allowed=No) (All),(All) | 0
Un-Routed Net Constraint ( (All) ) | 0
Modified Polygon (Allow modified: No), (Allow shelved: No) | 0
Width Constraint (Min=0.1mm) (Max=6mm) (Preferred=0.254mm) (All) | 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.21mm) (Air Gap=0.21mm) (Entries=4) (All) | 0
Hole Size Constraint (Min=0.025mm) (Max=10mm) (All) | 0
Hole To Hole Clearance (Gap=0.2mm) (All),(All) | 0
Minimum Solder Mask Sliver (Gap=0.06mm) (All),(All) | 0
Net Antennae (Tolerance=0mm) (All) | 0
Matched Lengths(Tolerance=2mm) (InNetClass('DIFF90')) | 0
Room IPD (Bounding Region = (294.791mm, 270.129mm, 295.869mm, 271.614mm) (False) | 0
Room CSP (Bounding Region = (293.893mm, 265.755mm, 296.052mm, 268.287mm) (False) | 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) | 0
Total | 0