******************************************************************************
* @file    readme.txt
* @author  Application Hardware Board
* @version 2.0
* @date    23-September-2024  
* @brief   DDR memory routing examples for STM32MP13x product lines
******************************************************************************
* COPYRIGHT(c) 2024 STMicroelectronics
*
* The Open Platform License Agreement (“Agreement”) is a binding legal contract
* between you ("You") and STMicroelectronics International N.V. (“ST”), a
* company incorporated under the laws of the Netherlands acting for the purpose
* of this Agreement through its Swiss branch 39, Chemin du Champ des Filles,
* 1228 Plan-les-Ouates, Geneva, Switzerland.
*
* By using the enclosed reference designs, schematics, PC board layouts, and
* documentation, in hardcopy or CAD tool file format (collectively, the
* “Reference Material”), You are agreeing to be bound by the terms and
* conditions of this Agreement. Do not use the Reference Material until You
* have read and agreed to this Agreement terms and conditions. The use of
* the Reference Material automatically implies the acceptance of the Agreement
* terms and conditions.
*
* The complete Open Platform License Agreement can be found on www.st.com/opla.
******************************************************************************

========================
* History
========================

* 1.0 - 16-November-2022
------------------------
    + Official release.

* 2.0 - 23-September-2024
------------------------
    + new PCB STM32MP13XXAE_1DDR3Lx16 with correction on track length ''DDR_WEN''. Increase of 47 microns to avoid warning in the DDR track lengths excel file.
      Previous PCB version is functional. Modification is only done to avoid excel warning.	


========================
* Package content 
========================
    + STM32MP13XXAE (LFBGA289 14x14)
	- track lengths of STM32MP13XXAE
	- schematics, track lengths file, 4 layer PCB layout, BOM and gerber of STM32MP13XXAE_1DDR3Lx16 power discrete to support LPLV-STOP + 650MHz (same DC/DC for VDDCPU & VDDCORE)
        - schematics, track lengths file, 4 layer PCB layout, BOM and gerber of STM32MP13XXAE_LPDDR2 STPMIC1E
        - schematics, track lengths file, 4 layer PCB layout, BOM and gerber of STM32MP13XXAE_LPDDR3 STPMIC1E

    + STM32MP13XXAF (TFBGA320 11x11)
	- track lengths of STM32MP13XXAF 
	- schematics, track lengths file, 4 layer PCB layout, BOM and gerber of STM32MP13XXAF_1DDR3Lx16 STPMIC1D
	- schematics, track lengths file, 4 layer PCB layout, BOM and gerber of STM32MP13XXAF_LPDDR2 STPMIC1E
        - schematics, track lengths file, 4 layer PCB layout, BOM and gerber of STM32MP13XXAF_LPDDR3 STPMIC1E

    + STM32MP13XXAG (TFBGA289 9x9)
	- track lengths of STM32MP13XXAG 
	- schematics, track lengths file, 6 layer PCB layout, BOM and gerber of STM32MP13XXAG_1DDR3Lx16 power discrete to support LPLV-STOP2 + No LPLV-STOP + 650MHz + 900MHz
   	- schematics, track lengths file, 6 layer PCB layout, BOM and gerber of STM32MP13XXAG_LPDDR2 STPMIC1E
        - schematics, track lengths file, 6 layer PCB layout, BOM and gerber of STM32MP13XXAG_LPDDR3 STPMIC1E
  
******************* (C) COPYRIGHT 2024 STMicroelectronics *****END OF FILE
